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A 4th-Order Continuous-Time $DeltaSigma$ Modulator with Improved Clock Jitter Immunity using RTZ FIR DAC

机译:使用RTZ FIR DAC改善时钟抖动抗扰度的4 阶连续时间 $ Delta Sigma $ 调制器

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This paper highlights the influence of the main feedback DAC non-idealities affecting the performance of Continuous-Time Delta-Sigma Modulators (CTDSMs) in radio receiver Internet-of-Things (IoT) applications. It proposes the combination of the Return-To-Zero (RTZ) DAC pulse and Finite-Impulse-Response (FIR) DAC to have inherent Inter-Symbol-Interference immunity and reduced clock jitter sensitivity, which is crucial to meet the strict linearity and Signal-To-Noise-Distortion-Ratio (SNDR) requirements for integrated IoT radio receivers. The proposed design is validated through MATLAB® Simulink® simulations, showing that a 4th order single-bit CTDSM with RTZ + FIR DAC can achieve an SNDR performance only 3dB below the ideal even in the presence of 4.2 ps rms of clock jitter at 24 MHz sampling frequency in a 250 kHz signal bandwidth.
机译:本文重点介绍了主要反馈DAC非理想因素对无线电接收机物联网(IoT)应用中连续时间Delta-Sigma调制器(CTDSM)性能的影响。它提出了归零(RTZ)DAC脉冲和有限脉冲响应(FIR)DAC的组合,具有固有的符号间干扰抗扰性和降低的时钟抖动灵敏度,这对于满足严格的线性度和可靠性至关重要。集成IoT无线电接收器的信噪比(SNDR)要求。拟议的设计通过MATLAB®Simulink®仿真进行了验证,结果表明4 即使在250 kHz信号带宽,24 MHz采样频率下存在4.2 ps rms的时钟抖动时,带有RTZ + FIR DAC的高阶单比特CTDSM只能实现比理想状态低3dB的SNDR性能。

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