A 20-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Jitter Immunity Improved Full Clock Period SCR (FSCR) DAC and High-Speed DWA

摘要

A 20-MHz bandwidth continuous-time (CT) sigma-delta modulator (SDM) with third-order active-RC loop filter and 4-bit quantizer is implemented in a 0.13-$mu{hbox{m}}$ CMOS process. The immunity to clock jitter is greatly improved by employing full clock period switched-capacitor-resistor (FSCR) digital-to-analog converter (DAC) for feedback. A new data weighted averaging (DWA) technique is developed to remove the timing bottleneck at 640 MHz clock frequency. The CT SDM achieves 63.9 dB peak signal-to-noise-and-distortion ratio (SNDR) and 68 dB dynamic range (DR) which decreases by only 2.3 dB when the RMS jitter of the 640 MHz clock is 15.6 ps. The power consumption is 58 mW from a 1.2-V supply.