Flexible and Resource Efficient FPGA-Based Quad Data Rate Memory Interface Design for High-Speed Data Acquisition Systems

摘要

Data acquisition is the process of collecting digital data produced by various types of electronic devices, such as sensors, analog to digital converters (ADCs), communication interfaces and digital I/O modules. FPGAs are the most common data acquisition platform for implementation, as they provide a generic environment for different types of interfaces and supplementary logic elements for further processing. This paper presents a flexible and resource efficient data acquisition system implementation on FPGAs especially targeted for high bandwidth interfaces. The implementation details are based on a QDR (Quad Data Rate) Memory interface design, as QDR interface reveals the common characteristics of high speed data channels. Also QDR memories have a wide application area such as the network processor, baseband processor and other high performance parallel processing network and communication. Proposed interface is fully tested and verified on a custom board between XILINX XC7V980T-1 FPGA and CYPRESS CY7C2665KV18-450BZI QDRII+ memory. The methodology described for the QDR memory interface design can be directly utilized for data acquisition systems requiring similar high speed DDR interfaces, such as high speed ADCs and I/O demultiplexer chips.