Design of a Low Noise Clock Generator Based on TSMC65nm Process

摘要

This paper designed a low noise 14 GHz phase-locked loop (PLL) for high-speed serial interface. We use a differential structure with a feedback charge pump to reduce the system's common-mode noise and current mismatch. To further reduce the phase noise, a differential structure of the third-order filter is introduced, which can also decrease the chip area. By using a differential control capacitor, the nonlinear of the VCO can be alleviated. The PLL adopts TSMC 65nm CMOS technology, and the working voltage of the system is 1.1v. Simulation results show that the PLL locking time is 800ns and the phase noise of the VCO is 107dBc/Hz at 1MHz.