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Fractional clock generator with low power and low noise
Fractional clock generator with low power and low noise
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机译:具有低功耗和低噪声的分数时钟发生器
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摘要
A clock generator comprise a delta-sigma modulation, DSM, for generating a division control signal and a phase control signal, an oscillator, for generating an oscillation signal with a first frequency, an adjustable frequency divider, for performing a division operation on the oscillation signal according to the division control signal, to generate a first division signal and a second division signal with a second frequency, and a phase interpolator, PI, for performing a phase interpolation operation on the first and second division signals according to the phase control signal, to generate an output signal with an output frequency, wherein the first frequency is greater than the second frequency.
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