Assessment of IBIS Modeling Techniques without and with Package Parasitics for Signal Integrity Analysis Using Sigrity, HyperLynx and ADS

摘要

In this paper the IBIS (Input/output Buffer Information Specification) is employed to estimate the adverse effects of package parasitics, where some modifications are proposed in representation. The key feature of IBIS modeling is the ability to protect the proprietary information and to reduce simulation speed compared with other traditional modeling techniques like SPICE modeling. IBIS modeling has been a standard file type for the system designers in the industry because of several advantages over other modeling techniques. Many circuit designers, simulators and many vendors produce, use and are accepting these standards. Generation of IBIS models from spectre design of a typical digital buffer without and with package parasitics effects is investigated in this paper. By considering the package parasitics effects, the IBIS modeling represents the behavior of I/O buffer of the digital circuit. IBIS model generation strategies to incorporate package effects are validated with the spectre model to provide a suitable approach. The parasitics adverse effect of the package can be high for propagation delay and overshoot voltage. In addition to this, in this article we will be discussing about the accuracy of IBIS models with Signal integrity tools like Sigrity, HyperLynx and ADS is investigated.