Design and Implementation of Hardware Firewall Using FPGA

摘要

This paper presents FPGA based implementation of a hardware firewall. This is characterized by filtering of high speed packet of length 512 bits based on the list of allowed Internet Protocols. Designed FPGA hardware firewall consists of input register of 512 bits and output register of 512 bits. When the first packet enters the hardware firewall it takes 512 clock cycles to completely fit in input register. Many comparison statements are implemented as per the number of allowed IPs and then the matched packet will be given out through output register of 512 bits. Thus the first packet experiences total delay of 1024 clock cycles and by the time first packet comes out through output register the next packet enters in the input register at the same time and the process continues. The designed architecture is so has to achieve same processing time despite increasing the number of rules. The implementation results show that hardware based firewall is faster as compared to conventional software firewall.