Reducing SNV defect rates and wafer TAT in high volume semiconductor manufacturing

摘要

In the semiconductor industry, fabrication facilities constantly work towards maximizing the productivity of their capital equipment as they ramp manufacturing. IC fabs want inspection and review systems to reliably and quickly recognize defect excursions, facilitate root-cause defect analysis, and function faster and more efficiently. [1] One of the main challenges for Defect Review is dealing with false alarms. False alarms consume resources and delay manufacturing ramps, while missed defect excursions can result in millions of dollars' worth of scrapped parts and wasted engineering time. These false positives and false negatives increase manufacturing cycle time and delay time to market. This paper details the work conducted at a major US-based customer — Samsung Austin Semiconductors (SAS) — and explains how sharing wafer definitions between defect inspection tools and SEMVision defect review tools has increased defect capture rates, decreased false alarms, and reduced automatic SEM review cycle time. This paper also demonstrates how a unique method called “Product Share” was used to increase the productivity and reliability of Applied Material's SEMVision defect review systems. After “Product Share” was implemented and the results were monitored for 18 months, it was indicated and proved that SEMVision Non-Visual (SNV) defects and TAT (Turn-Around Time) were significantly reduced.