High output power frequency doubler for digital PLLs in fully integrated 24 GHz CMOS radar systems

摘要

In this paper, the design and optimization of a high output power 12-to-24 GHz CMOS microwave doubler intended as subsequent block of a digital PLL is presented. The active core consists of a switch pair operating in the subthreshold region and an amplifying common-gate transistor. For the design and optimization process an efficient analysis of the nonlinear circuit is introduced. By optimizing transistor size and layout the rectifying behavior is improved such that output power and efficiency achieve their maximum values. A transformer BALUN is used to transform the 100 Ohm differential output to the optimum load impedance. The doubler is realized in 65 nm CMOS technology. More than 0 dBm output power at 24 GHz has been achieved while the maximum power consumption remains below 17 mW. The rejection of the fundamental frequency is higher than 20 dB. The die incorporates ESD-protection and can be operated at a single voltage. The total die size is 600 μm by 400 μm.