Analysis and design of classical controllers in discrete time to reduce output impedance in UPS's

摘要

This paper presents the limitations of classical controllers in discrete time in reducing the output impedance of a single-phase inverter voltage source for UPS. The controller design methodology for a topology with the feedback of the inductor current and the capacitor voltage of the output L-C filter is proposed. This proposal considers the performance requirements for UPS, established in the standards IEC62040-3 and IEC61000-2-2. The validity was analyzed by an experimental prototype of 2kVA.