A low-power on-chip calibration technique for pipelined ADCs

摘要

This paper proposes a new low-power on-chip calibration technique, called One-Time Calibration. Compare to the traditional calibration techniques our calibration circuit is realized fully on-chip which consumes very little power and small chip area; besides it needs no auxiliary circuits at all during the conversion. A 10-Bit 200MSps pipelined ADC using our new calibration technique is designed in a 55-nm CMOS technology. The on-chip calibration circuit only consumes a power of less than 5mW and increases the analog core chip area only by 10%. The post simulation results show that the ADC reaches an ENOB of 9.0-Bit after calibration for all conditions (-40-+85°C, ±10% VDD) at Nyquist rate.