Improved Static Timing Path Analyzer for DSCH Tool

摘要

Timing, is the most important factor from all field and analysis of timing measurement is also essential before actual implementation. In Deep Sub Micron (DSM) era miniaturization of transistor size comprises in increasing the complexity of digital circuit design. As we know that in VLSI domain there is always trade-off among power, area, speed and cost but the performance of a design depends on the execution speed of the designed circuit. The trade-off between power, area can be compromised but no compromise in timing. So successful development of ASIC depends on accurate modeling of its operation. Designing a circuit to be logically correct is simple whereas producing an accurate timing model is critical. IC's are computer representation of the physical device so the designer's role is to design models characteristics with precise accuracy as actual silicon behaves. CAD tools are designed to offer an automation of process, as the designer is still a human being who controls how the tool will perform. Therefore CAD tools are also susceptible to GIGO: Garbage In Garbage Out, Phenomenon. Timing analysis is also an integral and important part of ASIC design flow. As there are number of EDA tools that supports timing analysis. DSCH is a subpart of microwind chip design EDA tool, specialized in schematic digital circuit design that also supports timing analysis. This paper describes the theory of static timing analysis (STA) and its design and implementation in DSCH tool.