对全速测试中时序例外路径的处理方法的改进

摘要

The high clock speeds and small geometry sizes found in today’s integrated circuits have led to an increase in speed related defects, so more and more companies have turned to at-speed test techniques to help ensure high test and product quality. Due to incomplete timing information during Automatic Test Pattern Generation （ATPG）, it is possible that some at-speed patterns may activate paths which are not required to meet system speed, and these patterns may fail during production test. This paper explains the importance of using the timing path exceptions during ATPG and compare previous methods of handling these paths to a new method that provides higher test and product quality.%全速测试（at-speed ATPG）是现代电子设计中必需的一个重要环节。然而由于在做ATPG时,时序信息不完整,所以某些全速测试的向量会激活一些实际系统中不需要那么快时钟速度的路径,这样就会使得这些向量在芯片量产测试中无法通过,导致芯片良率的降低,而这些降低却是由测试的失误造成的。本文主要解释了时序例外路径（timing path exception）在全速自动测试向量生成（at-speed ATPG）中的重要性,以及如何使用时序例外防止芯片良率降低的误发生,并且结合工作中的实际项目对旧的处理时序例外的方法和新方法做了比较,结果证明采用新方法可以使测试向量的覆盖率增加,被屏蔽的测试单元减少。