CLOCK GATING FOR X-BOUNDING TIMING EXCEPTIONS IN IC TESTING

摘要

An integrated circuit includes a clock gate that is used to prevent timing exception paths from affecting data being captured by scan chain registers during at-speed scan testing. A single clock gate can be used to control multiple timing-exception paths, so the amount of X-bounding circuitry inserted into the IC can be drastically reduced compared to that required by conventional X-bounding methodologies.