An Efficient Hardware Accelerator for HS1-SIV Encryption Algorithm

摘要

Data security is a major concern for everyone in today's informational world. Encryption is the process of encoding messages or information in such a way that only authorized parties can read it. It is one of the major information security solutions. Hash Stream1-Synthetic Initialization Vector (HS1-SIV) is a recently developed and fast encryption algorithm. In this paper, we present a hardware accelerator for the HS1-SIV encryption algorithm. Our implementation relied on parallelism and pipelining to increase message encryption throughput. The hardware realization of HS1-SIV encryption algorithm involved designing a hardware data path and control unit, modeling the data path in System Verilog hardware description language, validating and synthesizing it using a 90nm hardware cell library. The proposed design was thoroughly verified using a System Verilog layered test bench. The proposed pipelined model is very efficient and can encrypt messages at the rate of 457 Gigabytes per second.