Low-power comparator in 65-nm CMOS with reduced delay time

摘要

In this paper, a high-speed and low-power latched comparator in a 65-nm CMOS process is presented. In our proposed structure, a latched circuit with an adjusted delayed-clock with no static power consumption is added to the conventional latch-type comparator in order to enhance the clock frequency and reduce the power consumption and the delay time. Therefore, the maximum clock frequency of our proposed structure is enhanced from 700 MHz to 1.7 GHz at 0.6 V. Furthermore, at the clock frequency of 700MHz (at 0.6 V), the power consumption and the delay time of our proposed structure have been decreased by 38% and 65% in comparison with the conventional structure, respectively. Also, other advantages of the conventional comparator as high-impedance input and rail-to-rail output swing are kept in the proposed structure. Finally, the Monte Carlo simulations demonstrate that our proposed structure is robust against the effects of mismatches.