A Design for Testability Method for k-Cycle Capture Test Generation

摘要

Area overhead for non-scan based design-for-testability methods using controller augmentation is small compared with those for full scan design methods. It has been reported that a test generation method for data-path circuits using easily testable functional time expansion models where status-signal sequences and control-signal sequences are added as constraints could achieve high fault coverage. Since the development cost of dedicated test generation using easily testable functional time expansion models is high, design-for-testability methods such that general sequential test generation can easily search circuit states which are equivalent to the time expansion models are required. In this paper, we propose a design-for-testability method for k-cycle capture test generation where partial scan designs and controller augmentation are combined. In the partial scan design, state registers in controllers and status signal registers which are the inputs of controllers are replaced with scan registers. As the results, test generation is freely able to transfer to invalid states of controllers. We design state transitions of invalid states such that hardware elements in data-path circuits are k-cycle testable.