Generalized net model of logic gates and circuits

摘要

As a continuation of the previous paper, here are presented two models of Generalized Nets (GN) - an n-bit digital magnitude comparator and an n-bit digital full adder. We can perform the measurements, if we have a set of several logical circuits that can be used to obtain identical output data. The aforementioned logical circuits must be composed of different logical elements. By using several measurement points and different schematics, we can suggest the best solution for the considered type of task.