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Review of percolating and neck-based underfills with thermal conductivities up to 3 W/m-K

机译:审查导热率高达3 W / m-K的渗流和基于颈部的底部填充

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Heat dissipation from 3D chip stacks can cause large thermal gradients due to the accumulation of dissipated heat and thermal interfaces from each integrated die. To reduce the overall thermal resistance and thereby the thermal gradients, this publication will provide an overview of several studies on the formation of sequential thermal underfills that result in percolation and quasi-areal thermal contacts between the filler particles in the composite material. The quasi-areal contacts are formed from nanoparticles self-assembled by capillary bridging, so-called necks. Thermal conductivities of up to 2.5 W/m-K and 2.8 W/m-K were demonstrated experimentally for the percolating and the neck-based underfills, respectively. This is a substantial improvement with respect to a state-ofthe-art capillary thermal underfill (0.7 W/m-K). Critical parameters in the formation of sequential thermal underfills will be discussed, such as the material choice and refinement, as well as the characteristics and limitations of the individual process steps. Guidelines are provided on dry vs. wet filling of filler particles, the optimal bi-modal nanosuspension formulation and matrix material feed, and the overpressure cure to mitigate voids in the underfill during backfilling. Finally, the sequential filling process is successfully applied on microprocessor demonstrator modules, without any detectable sign of degradation after 500 thermal cycles. The morphology and performance of the novel underfills are further discussed, ranging from particle arrangements in the filler particle bed, to cracks formed in the necks. The thermal and mechanical performance is benchmarked with respect to the capillary thermal and mechanical underfills. Finally, the thermal improvements within a chip stack are discussed. An 8or 16-die chip stack can dissipate 46% and 65% more power with the optimized neck-based thermal underfill than with a state-of-the-art capillary thermal underfill.
机译:3D芯片堆栈的散热会由于每个集成管芯散发的热量和热界面的积累而引起较大的热梯度。为了降低整体热阻,从而降低热梯度,该出版物将概述一些有关顺序热底部填充形成的研究,这些填充会导致复合材料中填料颗粒之间发生渗流和准区域热接触。准区域触点由通过毛细桥接自组装的纳米颗粒(所谓的颈部)形成。对于渗流和基于颈部的底部填充,分别通过实验证明了高达2.5 W / m-K和2.8 W / m-K的热导率。相对于最新的毛细管热底部填充胶(0.7 W / m-K),这是一个重大的改进。将讨论顺序热底部填充的形成中的关键参数,例如材料的选择和改进,以及各个工艺步骤的特征和局限性。提供了有关填料颗粒干式填充与湿式填充,最佳双峰纳米悬浮液配方和基质材料进料以及超压固化的指南,以减轻回填期间底部填料中的空隙。最后,顺序填充过程已成功应用于微处理器演示器模块,在经过500个热循环后没有任何可察觉的退化迹象。进一步讨论了新型底部填充胶的形态和性能,其范围从填充剂颗粒床中的颗粒排列到颈部形成的裂纹。相对于毛细管热和机械底部填充,对热和机械性能进行了基准测试。最后,讨论了芯片堆叠内部的散热改进。经过优化的基于颈部的热底部填充技术比采用最新技术的毛细管热底部填充技术,一个8芯或16芯芯片堆叠的功耗可高出46%和65%。

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