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TUTORIAL 02: Building in Reliability in Silicon Devices

机译:Tutorial 02:在硅设备中以可靠性构建

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As the device technology is progressing in the nanometer regime towards atomic scale, the famous comment “There is plenty of room at the bottom” by Richard Feynman about 60 years ago needs to be reviewed carefully and understood in detail. A recent comment “There is plenty of difficulty near the bottom” by device manufacturers depicts another face of the advancement in technology. The difficulty observed is in the path for building reliable devices. Device reliability is the resultant of various analyses of the design, process and product and understanding innumerable phenomenon to control the extension of even atomic level defects, especially when the dimensions are at nanometer level. At the early stages of technology development, the reliability estimation was through specific tests prediction to weed out defects. Many such tests are a routine and has helped to develop technology. However, at that time itself it was known that understanding device physics and solving the related problems at smaller dimensions are the key to success. As such, the device development at any technology level has been through the critical understanding of the failures through physical analysis and hence solving the issues. This procedure is the Building-in reliability in devices. It could be noted that many fundamental physics problems such as hot carriers, issues of dielectric breakdown and strength, electro migration and stress migration, electrostatic discharge issues, etc which paused the threat at different stages were solved fully or partially through physical failure analysis and understanding the related failure mechanisms. However, as the technology progressed with new materials at new dimensions, the problems also became more challenging. The tools which helped and being used for analysis itself have limitations due to the dimensional miniaturization. Moreover, the diversification in the manufacture from design to product through different vendors and stages invites a separate approach for building the product reliability. This tutorial discusses the fundamentals of reliability and failure analysis in its basic concepts and from where it can be understood using a physics based approach. The progression in devices from the conventional MOSFET and its dimensional shrinkage to nano scale MOSFET and then to new FinFET is discussed with a view to understand how the physical failure analysis can reveal the failure mechanisms to improve reliability. While evolving these processes to build reliability in nano scale devices, it is also understood that the fundamental problem remains the same as in early 1960s. That is where the “the plenty of room” is emerged as “plenty of difficulty”.
机译:由于设备技术在走向原子级纳米制度进步,著名评论“有足够的空间在底部”,由理查德·费曼大约60年前需要进行认真的审查,并详细了解。最近注释“有大量接近底部的困难”,由设备制造商描绘了技术进步的另一张面孔。观察到的困难是建立可靠的设备的路径。器件的可靠性是设计,加工和产品和理解无数现象来控制的,即使原子级的缺陷延伸的各种分析所得到的,特别是当尺寸在纳米级别。在技​​术发展的早期阶段,可靠性估计是通过特定的测试预测淘汰缺陷。许多这样的测试是一个常规,并帮助开发技术。但是,在那个时候它本身众所周知,理解器件物理和解决在较小尺寸的相关问题是成功的关键。因此,在任何技术水平的设备开发已通过通过物理分析,从而解决问题失败的批判性理解。本程序是在设备的建筑物中的可靠性。可以注意到,许多基本的物理问题,例如热载流子,其停在不同阶段的威胁通过物理失效分析和理解被完全或部分地解决了电介质击穿和强度,电迁移和应力迁移,静电放电问题等问题相关的失效机制。然而,随着技术与新的层面新材料的进展,存在的问题也变得更具挑战性。正在使用的帮助和工具,用于分析本身有局限性,由于尺寸小型化。此外,在从通过不同的供应商和阶段设计到产品制造中的多样化邀请建立了产品的可靠性一个单独的方法。本教程讨论的可靠性和失效分析的基本原理在其基本概念和从那里可以使用基于物理的方法来理解。在从传统的MOSFET和其尺寸收缩到纳米尺度MOSFET器件,然后进展到新的FinFET与视图了解物理失效分析可以如何显示故障机制来提高可靠性的讨论。虽然不断发展的这些方法在纳米尺度装置构建可靠性,还理解的是,基本问题仍然存在与在1960年代早期。这是其中的“足够的空间”被成为“很多难度。”

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