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Vivado HLS-based implementation of a fall detection decision core on an FPGA platform

机译:在FPGA平台上基于Vivado HLS的跌倒检测决策核心的实现

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New ultra-low power FPGAs provide system designers the flexibility to create completely customizable low-power solutions to bring new classes of applications to life. Fall detection is one of the major problems the elderly population is facing. This paper aims to present the design of an heterogeneous wearable system built with Zynq System-On-Chip (SoC) for fall detection. The design has been validated on ARM A9 processor for the software side and using Vivado High Level Synthesis (HLS) for hardware implementation on a Zynq-7010 SoC. The implementation results of the fall detection core showed less power consumed and 50% less on-chip logic resources used compared to the software implementation.
机译:新的超低功耗FPGA为系统设计人员提供了创建完全可定制的低功耗解决方案的灵活性,从而使新型应用程序栩栩如生。跌倒检测是老年人口面临的主要问题之一。本文旨在介绍采用Zynq片上系统(SoC)构建的异构可穿戴系统的设计,以用于跌倒检测。该设计已在ARM A9处理器上进行了软件方面的验证,并使用Vivado高级综合(HLS)在Zynq-7010 SoC上进行了硬件实现。与软件实现相比,跌倒检测内核的实现结果显示功耗更低,片上逻辑资源使用量减少了50%。

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