用Vivado HLS实现粒子滤波算法的硬件加速

摘要

Since the general development flow of hardware implementation for particle filter(PF)has the defect of long development cycles, tedious process, and poor flexibility, a new method based on Vivado high-level synthesis(HLS)is proposed, which synthesizes the particle filter algorithm descripted in C language into the RTL implementation directly and efficiently.This paper focuses on the application of two-dimensional bearings-only tracking(2-D BOT),applies several parallel pipeline optimization directives according to the data structure of Gaussian particle filter(GPF),and finally presents a FPGA module with high degree of parallelism.C/RTL cosimulation results show that this module can be used to solve the 2-D BOT problem with 1.5 times higher pro-cessing rate than that of simplified particle filters.At the same time,this new method of hardware implementation of particle filter has guiding significance for the hardware acceleration of other complex software algorithms.%针对传统现场可编程门阵列(field-programmable gate array,FPGA)开发流程中,以硬件实现粒子滤波算法(parti-cle filter,PF)的开发周期长、过程繁琐和灵活性差等缺陷,提出了一种基于Vivado高层次综合(high level synthesis,HLS)工具的PF算法硬件实现新方法,直接高效地将C语言描述的PF算法综合为RTL硬件模块.文中以二维纯方位跟踪(2 di-mensional bearing-only tracking,2-D BOT)为应用背景,以高斯粒子滤波(Gaussian particle filter,GPF)为目标算法,根据其数据结构,给出相应的并行流水线策略,综合出具有高并行度的FPGA运算模块.C/RTL协同仿真表明:该运算模块能较好实现对动目标的跟踪,并且能达到相当于简化粒子滤波器1.5倍的运算速度;同时该实现方法对其他复杂软件算法的硬件化加速具有指导意义.