Design and Analysis of a Low Power Digital Phase Locked Loop

摘要

This paper presents a novel architecture for digital phase locked loop. This architecture includes following modules: Low power phase and frequency detector (PFD) consumed 19.7nw at 90nm technology node, time to digital converter (TDC) to reduce error in phase of the input signal, digitally controller oscillator (DCO) to synthesize RF frequencies in deep submicron CMOS process. All modules are integrated in order to reduce locking range and to minimize jitter.