Low Power Consumption Based 4T SRAM Cell for CMOS 130nm Technology

摘要

In the Recent time, SRAM became a major component for many VLSI Chips due to big storage memory and low access time. Power Consumption is the major issue for design the SRAM CMOS design System on Chip. Power consumption also effects the chip design and Speed of the SRAM. In this paper, we propose 4T SRAM Cell which is able to reduce the power consumption and Area also. As we can see from the results session, power consumption of the 4T SRAM Cell get reduce up to 36% as compare to 6T SRAM Cell.