All-Digital High-Speed Wide-Range Binary Detecting Pulsewidth Lock Loops

摘要

This paper proposed a novel all-digital pulsewidth lock loops which adopted cyclic binary pulsewidth detector and cyclic delay line mechanism. This design has reduced the circuit area of delay line length increase under lower frequency operation, and it utilizes binary pulsewidth detection to lock output pulsewidth rapidly, whose locking time costs in only 25 duty cycles. Moreover, two delay lines is adopted in the pulsewidth generation mechanism circuit, and the cyclic delay line is employed under low frequency operation, but bypassed under high frequency operation for simplifying pulsewidth generating path. The output pulsewidth 25, 50, 75 % (by setting) could be generated by shift register, and the operating frequency range is 100 MHz to 3 GHz at CMOS 90 nm process simulation.