An data pattern optimized method for simultaneous switching noise suppression and good signal integrity in high speed system design

摘要

In this paper, a new optimized data pattern method is proposed to suppress the simultaneous switching noise (SSN) by controlling the switching intra delay between IOs, which will result in better signal integrity (SI) with less capacitors and less chip area consumption based on the periodic characteristics of the switching current and the SSN produced by one current pulse. It is found that the SSN period is determined by the resonant frequency and SSN can be suppressed by adjusting the IO switching delay to average the charge requirement for power delivery network (PDN), which is verified by simulations of lumped circuit model and distributed model. Good SI could also be obtained due to low noisy power supply voltage.