Carry Select Adder (CSLA) is the best and effective adder utilized in digital signal processing to implement high-speed arithmetic applications. CSLA adder will solve fast arithmetic functions in multiple data processing methods. CSLA method is mainly used to diminish the power and area instead of using normal adder. This adder is influenced by many system structures to avoid the carry delay. The main intention of this paper is to use Binary to Excess-1 Converter (BEC) instead of Ripple Carry Adder (RCA) with Cin = 1 in the normal CSLA to get high-speed operations, small area, and low power utilization. Here, binary excess converter will become the number of minor logic gates when compared to n bit Full Adder (FA) structure. According to this deliberation, the delay of time also will be reduced. In this paper, the proposed BEC method will give the significant results with regard to reducing power and area. The CMOS process technology is implemented on 0.18 m custom design and layout.
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