Low power high speed area efficient Error Tolerant Adder using gate diffusion input method

摘要

In digital VLSI circuits, perfectly accurate outputs are not always needed. So designers have started to design error tolerance circuits which provide good enough output for computation. On the basis of this fact, error tolerant adder (ETA) is designed which provides a way to achieve good power and speed performance. In this paper, an emerging logic style of circuit design, gate diffusion input (GDI) technique is adopted to design a 32-bit ETA. The proposed design reduces area in terms of area the transistor count to a great extent as well as improves the delay and power performance. Simulation results have shown that proposed design achieves 38% improvement in the Power-Delay-Product when compared to the existing design.