Design of reversible 32-bit BCD add-subtract unit using parallel pipelined method

摘要

Arithmetic unit design using reversible logic gate has received much attention as it reduces power dissipation with no loss of information. This paper proposes the design of 32-bit Binary Coded Decimal (BCD) addition and subtraction unit using reversible logic gates. The reversible 32 -bit BCD addition unit is designed using the following modules such as reversible 4-bit Carry Propagate unit using reversible logic gates such as Feynman gate and URG gate and a reversible 4-bit error correction unit. The 4-bit error correcting unit designed by reversible (4×1) Multiplexer (MUX) unit using Toffoli gate and TNOR gates to provide the output with a precise value. The reversible 32-bit BCD subtraction unit is designed based on the nine's complement method of 4-bit reversible BCD addition. In BCD subtraction unit, the error correcting block is designed with the conditional reversible logic COG gate to make the necessary corrections at the output to get exact output. The reversible 32-bit BCD addition and subtraction unit is designed based on the parallel pipelined unit to enhance the speed of operation. This proposed reversible 32-bit BCD addition module has 416 garbage values with the critical path delay of 17.420 ns; reversible 32-bit BCD subtraction module has 240 garbage values with the critical path delay of about 17.420 ns.