This paper presents the architecture of a modular element for the design of shared buffer ATM switch fabrics. The component is designed for deployment in a bit-sliced approach, and includes mechanisms to allow the number of elements in the fabric to be matched to the required aggregate bandwidth of the switch. All of the input ports must be synchronized to a Start of Cell input signal; the output ports optionally can be synchronized via an Output Hold signal. A bus forwards a portion of each incoming cell to a separate controller for identification and prioritization of the corresponding output operations. In addition to supporting width expansion for increased bandwidth, the component is designed to support depth expansion for more cell storage capacity at a given aggregate throughput. The component includes 32 one-bit inputs, 32 one-bit outputs, and 4 megabits of static RAM storage. Eight of the 100 MHz devices comprise a 32 port ATM switch fabric with an aggregate bandwidth of 20 gigabits per second and a storage capacity of 64 K/spl times/512 bits.
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