Design and optimization of asynchronous circuits with gate-level pipelining

摘要

We have been working for asynchronous control with fine-grain pipeline circuits, namely, self-synchronous circuits. We have demonstrated self-synchronous FPGA and self-synchronous RSA crypt-engine, to show energy consumption reduction at the energy minimum operating point, by gate-level power gating, and tamper resistivity of crypt-engine by dual-rail asynchronous operations. It is, however, realized by custom design. This paper presents several trials for automated design optimization of the self-synchronous circuits.