Effect of semiconductor devices' output parasitic capacitance on zero-current clamping phenomenon in PWM-VSI drives

摘要

In voltage source inverter drives (VSI), in order to avoid a shoot through in DC link due to the finite turn on and turn off times of the semiconductor devices a dead-time is inserted. Even though this dead-time is imperative it causes several aberrations in the output current waveform. Not only it gives rise to odd order harmonics but also it influences zero-current clamping. This paper investigates zero-current clamping phenomenon in a generic sense where output parasitic capacitance is in existence. The effects on voltage, power and torque due to the output parasitic capacitance is discussed. Simulations are carried out under practical conditions and results are presented. Results verify the credibility of the analysis.