A 12-b 100MS/s low-power successive approximation register ADC in 65nm COMS

摘要

This paper presents a 12 bit 100 MS/s relatively low-power successive approximation register (SAR) analog-to-digital converter (ADC). On the basis of typical structure of SAR ADC, some effective techniques such as high speed low noise dynamic comparator to reduce power dissipation, bootstrapped sampling-switch to suppress nonlinear distortion, novel push-pull buffer to enhance the conversion accuracy have been employed. Pre-simulation achieves 11.77 ENOB. Moreover, post-simulation result demonstrates that the proposed ADC achieves a peak SNDR of 67.41dB (ENOB=10.91 bit) at 100MS/s sampling rate and consumes 5.96mW. With the 65nm COMS process the ADC core occupies an active area of 0.36mm×0.25mm.