Design of 3-stage high frequency CMOS voltage controlled oscillators

摘要

This paper suggests a three stage voltage controlled oscillator designed using 0.18μm CMOS process with maximum oscillation frequency up to 4.7GHz. Suggested VCO have high tuning range, linear frequency voltage characteristics, low power consumption and have low phase noise. A tail current improvement technique is applied to reduce the discharging time. Oscillation frequency varies from 4.7GHz–0.500GHz when the controlled voltage varies from 1.8V to 0.5V respectively. Prototype was designed in Cadence Virtuoso environment and implemented using gpdk 180nm library with power supply at 1.8V. The measured phase noise for the circuit is −147.1 ldBc/Hz at a 1-MHz offset from a 3.9 GHz centre frequency. Simulated Power consumed by the design is 0.949 mW at 3.38 GHz.