MASH Delta Sigma ADC layout for dual mode GSM WLAN application

摘要

Analog to Digital Converter (ADC) is a component which transforms analog signals into digital signals. This paper focused on designing oversampling ADC with Delta-Sigma modulator which will be used in GSM and WLAN baseband communication system. The proposed Delta-Sigma ADC is divided into three main parts, which are pre-processing, modulator, and post-processing modules. Pre-processing module has important role in converting the input signal, which has continuous value continuous time characteristic, to be discrete time continuous value signal. Modulator is needed to process the signal from pre-processing module to be pulse signal, while post-processing module will convert the pulse signal into digital signal. The pre-processing part is implemented by sample and hold circuit. Modulator is designed using cascaded modulator topology - a number of four modulators are cascaded with MASH 2-1-1-1 configuration. Each modulator's block has feedback topology with 1-bit quantizer and works in discrete time domain. Hence, ADC system is implemented in layout of 180 nm technology, which consists of OTA, capacitor, comparator, and digital logic circuit. Decimation Filter of 5-stage CIC filter is needed for the implementation of postprocessing module.