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A 0.13 μm CMOS adaptive sigma–delta modulator for triple-mode GSM/Bluetooth/UMTS applications

机译:用于三模GSM /蓝牙/ UMTS应用的0.13μmCMOS自适应sigma-delta调制器

摘要

This paper describes the design and experimental characterization of a 0.13 μm CMOS switched-capacitor reconfigurable cascade ΣΔ modulator intended for multi-standard GSM/Bluetooth/UMTS hand-held devices. Both architectural- and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt the effective resolution and the output rate to different standard specifications with optimized power dissipation. This is achieved by properly combining different reconfiguration modes that include the variation in the order of the loop filter (3rd- or 4th-order), the clock frequency (40 or 80 MHz), the internal quantization (1 or 2 bits), and the bias currents of the amplifiers. The selection of the modulator topology and the design of its building blocks are based on a top-down CAD methodology that combines simulation and statistical optimization at different levels of the modulator hierarchy. Experimental measurements show a correct operation of the prototype for the three standards, featuring dynamic ranges of 83.8/75.9/58.7 dB and peak signal-to-(noise+distortion) ratios of 78.7/71.3/53.7 dB at 400 ksps/2/8 Msps, respectively. The modulator power consumption is 23.9/24.5/44.5 mW, of which 9.7/10/24.8 mW are dissipated in the analog circuitry. The multi-mode ΣΔ prototype shows an overall performance that is competitive with the current state of the art.
机译:本文介绍了用于多标准GSM /蓝牙/ UMTS手持设备的0.13μmCMOS开关电容器可重构级联ΣΔ调制器的设计和实验特性。芯片中集成了架构级和电路级重配置策略,以使有效分辨率和输出速率适应不同的标准规格,并优化功耗。这是通过适当地组合不同的重配置模式来实现的,这些重配置模式包括环路滤波器的阶数(3阶或4阶),时钟频率(40或80 MHz),内部量化(1或2位)和放大器的偏置电流。调制器拓扑的选择及其构建模块的设计基于自上而下的CAD方法,该方法结合了调制器层次结构不同级别上的仿真和统计优化。实验测量表明,这三种标准样机均能正确运行,其动态范围为83.8 / 75.9 / 58.7 dB,在400 ksps / 2/8时的峰值信噪比(噪声+失真)为78.7 / 71.3 / 53.7 dB分别为Msps。调制器功耗为23.9 / 24.5 / 44.5 mW,其中9.7 / 10 / 24.8 mW消耗在模拟电路中。多模ΣΔ原型显示出总体性能,与目前的技术水平相比具有竞争力。

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