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Demonstration of TCNCP flip chip reliability with 30#x03BC;m pitch Cu bump and substrate with thin Ni and thick Au surface finish

机译:演示了具有30μm节距的Cu凸点和具有薄Ni和厚Au表面光洁度的衬底的TCNCP倒装芯片可靠性

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Recently, TCNCP (Thermal Compression with Non-Conductive Paste) flip chip technology has been adopted for various devices because of high demand for large bump density. Fine pitch micro Cu bumps are usually connected to trace on the substrate (Bump on Trace, BOT) due to space limitation on substrate. In this study, TCNCP technology was used to attach die onto substrate trace with surface finish of thin Ni (0.1um) and thick Au (0.4um). The micro Cu bump used in the device under test has a dome shaped Sn-based solder cap of 13um in height. The ratio of Au layer plated on the substrate trace to Sn cap on the Cu bump is about 10 wt%, which is far beyond threshold value of 3 wt% for Au embrittlement. However, it was proved that the micro joint obtained with TCNCP can pass TCT 1000 cycles, HTS 1000hours and uHAST 192hrs without failure. SEM/EDX study on HTS samples (0hr, 500hr, 1000hr) showed that the joints had a large amount of IMC formed mainly consisting of (CuxAu1-x)6Sn5 phase after reflow and independent Cu3Sn phase formed near to die bump at a later stage during HTS test. Although AuSn4 was present in 0hr sample, it disappeared later. No Ni was detected. Phase segregation appeared near to die bump when HTS time went up to 1000hrs. No crack and void were found at that point.
机译:近来,由于对大凸块密度的高需求,TCNCP(具有非导电性糊剂的热压缩)倒装芯片技术已被用于各种器件。由于基板上的空间限制,通常将细间距的微型Cu凸块连接到基板上的走线(Bump on Trace,BOT)上。在这项研究中,TCNCP技术用于将管芯附着在具有细Ni(0.1um)和厚Au(0.4um)的表面光洁度的基板走线上。被测器件中使用的微型Cu凸块具有高度为13um的圆顶形Sn基焊料盖。镀在基板迹线上的Au层与Cu凸块上的Sn帽的比例约为10 wt%,这远远超出了Au脆化的3 wt%阈值。然而,事实证明,用TCNCP获得的微关节可以通过TCT 1000个循环,HTS 1000小时和uHAST 192小时而不会失败。对HTS样品(0hr,500hr,1000hr)进行的SEM / EDX研究表明,焊缝后形成大量的IMC,主要由(CuxAu1-x)6Sn5相组成,并在后期形成独立的Cu3Sn相并靠近芯片凸点在HTS测试中。尽管0h样品中存在AuSn4,但后来消失了。没有检测到镍。当高温超导时间达到1000小时时,相分离似乎快要消失了。此时未发现裂纹和空隙。

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