Fast evaluation of test vector sets using a simulation-based statistical metric

摘要

Evaluating the coverage of tests for large circuits is computationally very intensive, particularly for logic BIST, software-based self test and on-line test schemes. This has led to research into techniques for rapidly evaluating the coverage of proposed test. We introduce a new metric which is highly correlated with fault coverage measured by gate-level simulators. Based on this metric, we estimate the time when the fault coverage saturates. This is done with only one pass of simulation and it provides a measure of the effectiveness of the test sequence when applied to the circuit-under-test; additionally, the fault coverage can be estimated with a relatively small number of test vectors. Experimental results on the ISCAS'85 and ISCAS'89 benchmarks, and a RISC processor (OR1200), show an average error of 2.85% in the estimated fault coverage compared with the fault coverage from full fault simulation, with an average speedup over 8x for large circuits.