The hybrid frequency synthesizer based on DDS and two-loop PLL

摘要

Applying the PLL system as a multiplier of direct digital synthesizers (DDS) output frequency in hybrid frequency synthesizers was analyzed in this paper. Increasing of DDS output frequency helps to reduce the division ratio in the feedback loop and, as consequence, decrease the phase noise level. It was proved that the PLL multiplier makes a significant contribution to the phase noise level of the hybrid synthesizer. The comparison of noise performances of the hybrid synthesizer and two-loop PLL system was performed.