New high speed dynamic d-type flip flop for prescaler

摘要

We propose a new dynamic D-type-Flip-Flop(DFF) suitable for high speed prescaler. Prescaler and VCO are the main blocks determining the operating speed of PLL. PLL is important for frequency synthesizer in wireless system. Recently, wireless frequency band goes higher, therefore the higher speed of PLL is needed. In order to increase the speed of PLL, prescaler and VCO must be optimized for high speed. First of all, prescaler consists of DFFs. The previous DFFs had many MOS transistors. The more transistors Flip-Flops have, the slower operating speed because of clock loads and effective capacitance. Thus we reduced the effective capacitance by reducing the number of transistors to get a higher speed. We implemented DFF with only 6 MOS transistors. This proposed circuit is verified by HSpice. And it is implemented with 0.8μm CMOS technology. The proposed DFF operates up to 6.4GHz at SV.