Condition detector for digital control signal uses two edge-triggered D-type flip-flops controlled by different clock signals for sampling control signal and controlling resettable flip-flop

摘要

The condition detector has two edge-triggered D-type flip-flops (10,11) controlled by different clock signals (CLKS,CLKA) for sampling a control signal (CKE) indicating the condition, coupled on the output side via respective pulse elements (12,13) to a resettable flip-flop (15), providing a feedback signal for one of the memory elements.