Examination of voiding at the drain pad of high-power FETs

摘要

At high power component packages having high area contact surfaces, voiding commonly appear, especially using insulated metal substrate (IMS) printed circuit boards (PCBs). Due to financial aspects, vacuum soldering is desired to be avoided. Vapour phase soldering (VPS) is an adequate technology for these kind of high thermal capacity circuits. The aim of the experiments was to reveal some of the key effects causing voids at high area drain pad field effect transistors soldered onto aluminium-FR4 printed circuit boards by VPS. 4 different solder pastes and 9 stencil aperture designs were tested and evaluated concerning the size and the distribution of voids.