Limit cycle suppression technique using digital dither in delta sigma DA modulator

摘要

This paper proposes a digital dither technique to suppress limit cycles in a ΔΣ DA modulator. It uses an exclusive OR (XOR) gate at the modulator output and the digital dither is generated by another ΔΣD modulator. The resolution of the DAC following the modulator is 1-bit (instead of multi-bit) thanks to XOR gate usage, and the overall SNR does not degrade because the dither is added at the output and hence it is noise-shaped. Our MATLAB simulation and FPGA implementation results have verified the effectiveness of the proposed method.