On the performance of a hybrid memristor/MOS π-attenuator circuit

摘要

This paper describes a new embodiment of a variable n-attenuator circuit that uses MOS transistors as the shunt elements and a TiO memristor as the pass element. By taking advantage of the unique frequency response of the memristor, the architecture offers the potential of improved linearity over recent all MOS transistor design. Spice simulations using 0.13um CMOS BSIM3v3 transistor models and a SPICE model for the Hewlett Packard TiO memristor show that the memristor-based π-attenuator exhibits the expected linearity improvement compared to a monolithic CMOS π-attenuator circuit.