A high-resolution analog-to-digital converter design for sub-100 nm technology using folding-integration technique

摘要

To design a low-power, high-speed and high-resolution analog-to-digital converter (ADC) in sub-100 nm technology, this paper presents a technique using folding integration (F. I.) and digital calibration. We have compared the circuit simulation results with the ideal case (Matlab simulation results) and have done nonlinearity analysis. The effectiveness of the digital error correction is confirmed by simulations.