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Design Techniques for Analog-to-Digital Converters in Scaled CMOS Technologies

机译:比例CMOS技术中模数转换器的设计技术

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摘要

Analog-to-digital converters (ADCs) are analog pre-processing systems that convert the real life analog signals, the input of sensors or antenna, to digital bits that are processed by the system digital back-end. Due to the various issues associated with CMOS technology scaling such as reduced signal swings and lower transistor gains, the design of ADCs has seen a number of challenges in medium to high resolution and wideband digitization applications. The various chapters of this thesis focus on efficient design techniques for ADCs that aim to address the challenges associated with design in scaled CMOS technologies. This thesis discusses the design of three analog and mixed-signal prototypes: the first prototype introduces current pre-charging (CRP) techniques to generate the reference in Multiplying Digital-to-Analog Converters (MDACs) of pipeline ADCs. CRP techniques are specifically applied to Zero-Crossing Based (ZCB) Pipeline-SAR ADCs in this work. The proposed reference pre-charge technique relaxes power and area requirements for reference voltage generation and distribution in ZCB Pipeline ADCs, by eliminating power hungry low impedance reference voltage buffers. The next prototype describes the design of a radiation-hard dual-channel 12-bit 40MS/s pipeline ADC with extended dynamic range, for use in the readout electronics upgrade for the ATLAS Liquid Argon Calorimeters at the CERN Large Hadron Collider. The design consists of two pipeline A/D channels with four MDACs with nominal 12-bit resolution each, that are verified to be radiation-hard beyond the required specifications. The final prototype proposes Switched-Mode Signal Processing, a new design paradigm that achieves rail-to-rail signal swings with high linearity at ultra-low supply voltages. Switched-Mode Signal Processing represents analog information in terms of pulse widths and replaces the output stage of OTAs with power-efficient rail-to-rail Class-D stages, thus producing Switched-Mode Operational Amplifiers (SMOAs). The SMOAs are used to implement a Programmable Gain Amplifier (PGA) that has a programmable gain from 0-12dB.
机译:模数转换器(ADC)是模拟预处理系统,可将现实生活中的模拟信号(传感器或天线的输入)转换为由系统数字后端处理的数字位。由于与CMOS技术缩放相关的各种问题,例如减少的信号摆幅和较低的晶体管增益,ADC的设计在中高分辨率到宽带数字化应用中遇到了许多挑战。本文的各个章节都集中在针对ADC的高效设计技术上,这些技术旨在解决与CMOS规模化设计相关的挑战。本文讨论了三个模拟和混合信号原型的设计:第一个原型介绍了当前的预充电(CRP)技术,以在流水线ADC的乘法数模转换器(MDAC)中生成参考。在这项工作中,CRP技术专门应用于基于零交叉(ZCB)的流水线SAR ADC。拟议中的参考预充电技术通过消除耗电的低阻抗参考电压缓冲器,放宽了ZCB流水线ADC中参考电压生成和分配的功率和面积要求。下一个原型将描述具有扩展的动态范围的抗辐射的双通道12位40MS / s管道ADC的设计,该模块将用于CERN大型强子对撞机ATLAS液态氩量热仪的读出电子设备升级。该设计由两个流水线A / D通道组成,每个通道具有四个MDAC,每个MDAC的标称分辨率为12位,经验证具有一定的抗辐射能力,超出了要求的规格。最终原型提出了开关模式信号处理,这是一种新的设计范例,可在超低电源电压下以高线性度实现轨到轨信号摆幅。开关模式信号处理以脉冲宽度表示模拟信息,并用省电的轨到轨D类级代替OTA的输出级,从而产生开关型运算放大器(SMOA)。 SMOA用于实现可编程增益放大器(PGA),其可编程增益介于0-12dB之间。

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