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GAA-CNTFET based Single/Dual-Channel and Single/Dual-Chirality digital gates for High Speed and Low Power Application

机译:基于GAA-CNTFET的单/双通道和单/双行力数字栅极,用于高速和低功耗应用

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Gate All-Around Carbon Nanotube Field Effect Transistor (GAA-CNTFET) is one of the promising transistors to substitute traditional MOSFET. This paper presents universal logic gates based on GAA-CNTFET with different chiral indexes and different number of channel selection for high speed and low power digital application. The simulation tool is used for design and simulation of GAA-CNTFET based basic logic gates. The power consumption and total delay for basic logic gates is calculated for different chirality indexes and different channel selection. From our results, we report that when we increase the chiral vector of CNT; delay increases in digital logic gates. Single chirality (25, 25, 0) based digital logic gates provide minimum delay, similarly dual chirality (25, 22, 0) type digital logic gates exhibits minimum delay. Whereas (14, 14, 0) and (16, 14, 0) chirality delivers low power consumption.
机译:门全绕碳纳米管场效应晶体管(GaA-CNTFET)是替代传统MOSFET的有前途晶体管之一。本文介绍了基于GaA-CNTFET的通用逻辑门,具有不同的手性指标和不同数量的高速和低功耗数字应用的通道选择。仿真工具用于基于GaA-CNTFET的基本逻辑门的设计和仿真。基本逻辑门的功耗和总延迟是针对不同的性行为指标和不同的信道选择来计算的。从我们的结果中,我们报告说,当我们增加CNT的手性载体时;数字逻辑门的延迟增加。基于单人行道(25,25,0)的数字逻辑门提供最小延迟,类似的双手性(25,22,0)型数字逻辑门呈现最小延迟。虽然(14,14,0)和(16,14,0)人行道提供低功耗。

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