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GAA-CNTFET based Single/Dual-Channel and Single/Dual-Chirality digital gates for High Speed and Low Power Application

机译:基于GAA-CNTFET的单通道/双通道和单通道/双通道数字门,适用于高速和低功耗应用

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Gate All-Around Carbon Nanotube Field Effect Transistor (GAA-CNTFET) is one of the promising transistors to substitute traditional MOSFET. This paper presents universal logic gates based on GAA-CNTFET with different chiral indexes and different number of channel selection for high speed and low power digital application. The simulation tool is used for design and simulation of GAA-CNTFET based basic logic gates. The power consumption and total delay for basic logic gates is calculated for different chirality indexes and different channel selection. From our results, we report that when we increase the chiral vector of CNT; delay increases in digital logic gates. Single chirality (25, 25, 0) based digital logic gates provide minimum delay, similarly dual chirality (25, 22, 0) type digital logic gates exhibits minimum delay. Whereas (14, 14, 0) and (16, 14, 0) chirality delivers low power consumption.
机译:栅极全能碳纳米管场效应晶体管(GAA-CNTFET)是替代传统MOSFET的有前途的晶体管之一。针对高速低功耗数字应用,本文提出了基于GAA-CNTFET的通用逻辑门,具有不同的手性指数和不同的通道选择数量。该仿真工具用于基于GAA-CNTFET的基本逻辑门的设计和仿真。针对不同的手性指标和不同的通道选择,计算基本逻辑门的功耗和总延迟。从我们的结果中,我们报告说,当我们增加CNT的手性载体时;数字逻辑门的延迟增加。基于单手征性(25、25、0)的数字逻辑门提供了最小的延迟,类似地,双手征性(25、22、0)类型的数字逻辑门则表现出了最小的延迟。 (14、14、0)和(16、14、0)手性可降低功耗。

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