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Improving flip chip process for large 2.5D molded interposer

机译:改进大型2.5D模制插入器的倒装芯片工艺

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The demand for high-performance semiconductor products in line with the development of information technology industry continues to increase. However, fab node shrinkage, which led the development of semiconductor performance in the past, has reached its limit. As a result, the need for multi heterogeneous chip integration technology is rapidly increasing. 2.5D packaging using Si interposer is one of these. The biggest difficulty in the development of 2.5D packaging is to overcome the warpage of multi-chip (including HBM, chiplet, etc.) integrated interposer. The first challenge is improving warpage caused by increase in the size of the interposer. Increasing the number of integrated chips is essential for improving the performance of the 2.5D package. On the other hand, this causes an increase in the size of the interposer, and the warpage increases as well. The second problem is unique warpage shape of the interposer. Unlike the conventional monolithic chip, the 2.5D interposer exhibits a variety of unique warpage shapes depending on the design. So it's not enough to simply reduce the size of the warpage. These problems are limited in overcoming them through material composition and design, so a way to overcome them through process technology is needed. In this study, the warpage behavior of multi-chip integrated interposer was analyzed, and a novel bonding technique which handle highly warped interposer was studied. To prevent non-wetting during bonding process of very highly warped interposer we devised a novel technique which can bond the chips overcoming limit of warpage. The actual measured warpage was 182um that bonding was impossible with conventional mass reflow. To overcome this, continuous loads were applied on the top of the interposer and high activity flux was used to induce stronger solder collapse in the direction of the substrates. As a result, bonding with mass reflow was possible even in interposer with severe warpage.
机译:对高性能半导体产品的需求符合信息技术行业的发展继续增加。然而,Fab节点收缩,这导致了过去的开发半导体性能,已达到其极限。结果,对多种异构芯片集成技术的需求正在迅速增加。 2.5D使用Si插入器的包装是其中之一。 2.5D包装开发的最大困难是克服多芯片(包括HBM,小芯片等)集成插入器的翘曲。第一个挑战是提高因插入器尺寸的增加而引起的翘曲。增加集成芯片的数量对于提高2.5D包的性能至关重要。另一方面,这导致插入器的尺寸增加,并且翘曲也增加。第二个问题是插入器的独特翘曲形状。与传统的单片芯片不同,2.5D插入器根据设计表现出各种独特的翘曲形状。因此,简单地减少翘曲的大小是不够的。这些问题是有限的,因为通过材料组成和设计克服它们,因此需要通过工艺技术克服它们的方法。在这项研究中,分析了多芯片集成插入器的翘曲行为,并研究了一种处理高翘曲的中介器的新型粘接技术。为了防止在非常高度翘曲的插入器的粘合过程中进行非润湿,我们设计了一种新颖的技术,可以粘合克服翘曲的极限。实际测量的翘曲是182um,常规质量回流是不可能的。为了克服这一点,在插入器的顶部上施加连续载荷,并且使用高活性通量在基板的方向上诱导更强的焊料塌陷。结果,即使在具有严重翘曲的插入器中,也可以用质量回流键合。

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