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Exploring the Potential for Collaborative Data Compression and Hard-Error Tolerance in PCM Memories

机译:探索PCM存储器中的协作数据压缩和硬误差容差的潜力

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Limited write endurance is the main obstacle standing in the way of using phase change memory (PCM) in future computing systems. While several wear-leveling and hard-error tolerant techniques have been proposed for improving PCM lifetime, most of these approaches assume that the underlying memory uses a very simple write traffic reduction scheme (e.g., buffering, differential writes). In particular, most PCM prototypes/chips are equipped with an embedded circuit to support differential writes (DW) - on a write, only the bits that differ between the old and new data are updated. With DW, the bit-pattern of updates in a memory block is usually random, which limits the opportunity to exploit the resulting bit pattern for lifetime enhancement at an architecture level (e.g., using techniques such as wear-leveling and hard-error tolerance). This paper focuses on this inefficiency and proposes a solution based on data compression. Employing compression can improve the lifetime of the PCM memory. Using state-of-the-art compression schemes, the size of the compressed data is usually much smaller than the original data written back to memory from the last-level cache on an eviction. By storing data in a compressed format in the target memory block, first, we limit the number of bit flips to fewer memory cells, enabling more efficient intra-line wear-leveling and error recovery, and second, the unused bits in the memory block can be reused as replacements for faulty bits given the reduced size of the (compressed) data. It can also happen that for a portion of the memory blocks, the resulting compressed data is not very small. This can be due to increased data entropy introduced by compression, where the total number of bit flips will be increased over the baseline system. In this paper, we present an approach that provides collaborative operation of data compression, differential writes, wear-leveling and hard-error tolerant techniques targeting PCM memories. We propose approaches that reap the maximum benefits from compression, while also enjoying the benefits of techniques that reduce the number of high-entropy writes. Using an approach that combines different solutions, our mechanism tolerates 2.9× more cell failures per memory line and achieves a 4.3× increase in PCM memory lifetime, relative to our baseline state-of-the-art PCM DIMM memory.
机译:有限的写入耐力是在未来计算系统中使用相变存储器(PCM)的主要障碍。虽然已经提出了用于改善PCM寿命的多种磨损和硬误差的技术,但是这些方法中的大多数假设底层存储器使用非常简单的写入流量降低方案(例如,缓冲,差分写入)。特别是,大多数PCM原型/芯片配备有嵌入式电路以支持差分写入(DW) - 在写入时,仅更新旧数据和新数据之间不同的位。通过DW,存储块中更新的比特模式通常是随机的,这限制了利用架构级别(例如,使用诸如耐磨和硬误差容错等技术来利用所产生的比特模式的机会。本文重点介绍这种低效率,并提出了一种基于数据压缩的解决方案。采用压缩可以改善PCM存储器的寿命。使用最先进的压缩方案,压缩数据的大小通常比从最后级别缓存写回到存储器的原始数据。通过将数据存储在目标存储器块中的压缩格式中,首先,我们将位数翻转到更少的内存单元格,实现更有效的内部线路磨损和错误恢复,而第二个,第二个,内存块中的未使用位鉴于(压缩)数据的尺寸减小,可以重用作为错误位的替换。还可以发生用于存储块的一部分,所得到的压缩数据不是很小。这可能是由于压缩引入的数据熵增加,其中位翻转总数将在基线系统上增加。在本文中,我们提出了一种方法,该方法提供针对PCM存储器的数据压缩,差分写入,耐磨,耐磨和硬误差误差耐受技术的协作操作。我们提出了从压缩中获得最大效益的方法,同时也享有减少高熵写入数量的技术的好处。使用一种结合不同解决方案的方法,我们的机制容忍2.9倍的每个内存线的细胞故障,并且相对于我们基线最先进的PCM DIMM存储器实现了4.3倍的PCM内存寿命。

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